ADC setup
Parameter
Value
comment
Resolution
;
12b
10b
8b
6b
Data align
;
Right
Left
Scan Direction
;
Upward
Downward
External Trigger Source
;
TIM1 TRGO
TIM1 CC4
TIM2 TRGO
TIM3 TRGO
TIM15 TRGO
External Trigger edge
;
None
Rising
Falling
Rising / Falling
ADC clock
;
Asynchronous 14MHz
PCLK/2
PCLK/4
None = ADC clock asynchronous 14MHz
Continuous conversion
Offset Calibration
Enable ADC
Start Conversion
DeInit ADC before initialisation
Channel Scanning setup
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Active channels
Sampling time
;
1.5 ADC clock cycles
7.5 ADC clock cycles
13.5 ADC clock cycles
28.5 ADC clock cycles
41.5 ADC clock cycles
55.5 ADC clock cycles
71.5 ADC clock cycles
239.5 ADC clock cycles
Mode
;
Discontinuous mode
Continuous mode
Discontinuous = one trigger, one step in sequence, Continuous = one trigger, whole sequence
Overrun
;
Overrun On
Overrun Off
Overrun Off = last sample is holded until read, Overrunr On = unreaded samples are overwritten
Analog Watchdog setup
Use Analog Watchdog
Watchdog Enable
Watchdog Single Channel
;
Single Channel
All channels
High Threshold
Low Threshold
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Channel
Temperature Sensor, Vrefint and Vbat management function
Enable Temperature Sensor
Enable Vref channel
Enable Vbat channel
IRQ and DMA settings
ADC Ready
End of sampling
End of conversion
End of sequence
overrun
Analog watchdog
IRQ
DMA Enable
DMA Mode
;
Circular
One Shot