DMA1
Memory base address
Peripheral base address
Memory data size
Peripheral data size
Direction
Mode
Memory Incrementing Enable incrementing memory addres
Peripheral Incrementing Enable incrementing peripheral addres
Buffer Size Number of data to transfer
Priority
FIFO Mode Enable FIFO mode
FIFO Threshold
Memory Burst
Peripheral Burst
DeInit Deinitialize DMA before setup

Interrupt settings
Transfer complete
Half transfer complete
Transfer error
FIFO Error

DMA 1 - F407 - Only MEMORY transfers !

Peripheral
requests		 Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7
Channel 0 SPI3_RX SPI3_RX SPI2_RX SPI2_TX SPI3_TX SPI3_TX
Channel 1 I2C1_RX TIM7_UP TIM7_UP I2C1_RX I2C1_TX I2C1_TX
Channel 2 TIM4_CH1 I2S3_EXT_RX TIM4_CH2 I2S2_EXT_TX I2S3_EXT_TX TIM4_UP TIM4_CH3
Channel 3 I2S3_EXT_RX TIM2_UP
TIM2_CH3		 I2C3_RX I2S2_EXT_RX I2C3_TX TIM2_CH1 TIM2_CH2
TIM2_CH4		 TIM2_UP
TIM2_CH4
Channel 4 UART5_RX USART3_RX UART4_RX USART3_TX UART4_TX USART2_RX USART2_TX UART5_TX
Channel 5 UART8_TX UART7_TX TIM3_CH4
TIM3_UP		 UART7_RX TIM3_CH1
TIM3_TRIG		 TIM3_CH2 UART8_RX TIM3_CH3
Channel 6 TIM5_CH3
TIM5_UP		 TIM5_CH4
TIM5_TRIG		 TIM5_CH1 TIM5_CH4
TIM5_TRIG		 TIM5_CH2 TIM5_UP
Channel 7 TIM6_UP I2C2_RX I2C2_RX USART3_TX DAC1 DAC2 I2C2_TX

Used only on F42x and F43x devices

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