DMA2
Memory base address
Peripheral base address
Memory data size
Peripheral data size
Direction
Mode
Memory Incrementing Enable incrementing memory addres
Peripheral Incrementing Enable incrementing peripheral addres
Buffer Size Number of data to transfer
Priority
FIFO Mode Enable FIFO mode
FIFO Threshold
Memory Burst
Peripheral Burst
DeInit Deinitialize DMA before setup

Interrupt settings
Transfer complete
Half transfer complete
Transfer error
FIFO Error

DMA 2 - F407

Peripheral
requests		 Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7
Channel 0 ADC1 SAI1_A TIM8_CH1
TIM8_CH2
TIM8_CH3		 SAI1_A ADC1 SAI1_B TIM1_CH1
TIM1_CH2
TIM1_CH3
Channel 1 DCMI ADC2 ADC2 SAI1_B SPI6_TX SPI6_RX DCMI
Channel 2 ADC3 ADC3 SPI5_RX SPI5_TX CRYP_OUT CRYP_IN HASH_IN
Channel 3 SPI1_RX SPI1_RX SPI1_TX SPI1_TX
Channel 4 SPI4_RX SPI4_TX USART1_RX SDIO USART1_RX SDIO USART1_TX
Channel 5 USART6_RX USART6_RX SPI4_RX SPI4_TX USART6_TX USART6_TX
Channel 6 TIM1_TRIG TIM1_CH1 TIM1_CH2 TIM1_CH1 TIM1_CH4
TIM1_TRIG
TIM1_COM		 TIM1_UP TIM1_CH3
Channel 7 TIM8_UP TIM8_CH1 TIM8_CH2 TIM8_CH3 SPI5_RX SPI5_TX TIM8_CH4
TIM8_TRIG
TIM8_COM

Used only on F42x and F43x devices

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